04875160 is referenced by 79 patents and cites 7 patents.

Pipelined CPUs achieve high-performance by fine tuning the pipe stages to execute typical instruction sequences. Atypical instruction sequences result in pipeline exceptions. The disclosed method provides graceful exception handling and recovery in a micropipelined memory interface. The use of a memory reference restart command latch allows an implementation that requires no additional logic for conditional writing of states pending exception checking. The exception handling hardware is minimized because instructions which cause exceptions are never re-executed, and exception handling microcode executes in-line with the normal microcode flow.

Title
Method for implementing synchronous pipeline exception recovery
Application Number
7/221934
Publication Number
4875160
Application Date
July 20, 1988
Publication Date
October 17, 1989
Inventor
John F Brown III
Northborough
MA, US
Agent
Arnold White & Durkee
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 9/38
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