04868629 is referenced by 35 patents and cites 33 patents.

A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.

Title
Self-aligned split gate EPROM
Application Number
610369
Publication Number
4868629
Application Date
August 2, 1985
Publication Date
September 19, 1989
Inventor
Boaz Eitan
Sunnyvale
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
WaferScale Integration
CA, US
IPC
H01L 27/10
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