04861730 is referenced by 35 patents and cites 22 patents.

A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.

Title
Process for making a high density split gate nonvolatile memory cell
Application Number
7/147843
Publication Number
4861730
Application Date
January 25, 1988
Publication Date
August 29, 1989
Inventor
Wei Ren Shih
San Jose
CA, US
Pritpal S Mahal
San Jose
CA, US
Steve K Hsia
Saratoga
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
Catalyst Semiconductor
CA, US
IPC
H01L 29/78
H01L 27/10
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