04860192 is referenced by 82 patents and cites 65 patents.

In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascending locations of stored data from the cache memory. In an illustrated embodiment, the cache memory stores four words per addressable line of cache storage, and accordingly quad-word boundary registers determine boundary limits on quad-words, quad-word line registers store, in parallel, a selected line from the cache memory, and a quad-word boundary detector system determines when to prefetch the next set of quad-words from the cache memory for storage in the quad-word line registers.

Title
Quadword boundary cache system
Application Number
704497
Publication Number
4860192
Application Date
October 3, 1986
Publication Date
August 22, 1989
Inventor
Walter H Hollingsworth
Campbell
CA, US
James Y Cho
Los Gatos
CA, US
Howard G Sachs
Los Gatos
CA, US
Agent
Townsend and Townsend
Assignee
Intergraph Corporation
AL, US
IPC
G06F 13/00
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