04855672 is referenced by 64 patents and cites 13 patents.

Disclosed herein is a method and circuit useful in the testing of integrated circuit chips. On-chip test circuitry is provided at a selected location on an IC chip and energized while the chips are still mounted on a lead frame member, wound on reels and heated in an oven. Advantageously, the continuous lead frame member may be a tape automated bond (TAB bond) flexible circuit which is adapted for gang bonding to a large plurality of ICs before being wound on reels. In a preferred test circuit embodiment, the conductive on-off state of digital address circuitry is controlled by applying a test signal potential to an input test pad and through a fuse to a common test circuit junction. This junction is in turn connected between a transistor and diode in a series control network which is operative to control the conductive state of the address circuitry. This network enables the input test pad to be used as both a test signal input connection and a ground connection for the IC test circuit.

Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same
Application Number
Publication Number
Application Date
May 18, 1987
Publication Date
August 8, 1989
Robert W Shreeve
3650 NW. Elmwood, Corvallis, 97330
G01R 1/04
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