04853846 is referenced by 56 patents and cites 8 patents.

Control logic for controlling references to a cache (24) including a cache directory (62) which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory (62) for cache data-array addresses. A cache-configuration register and control logic (64) splits the cache directory (62) into two logical directories, one directory for controlling requests from a first processor and the other directory for controlling requests from a second processor. A prefetch buffer (63) is provided along with a prefetch control register for splitting the prefetch buffer into two logical channels, a first channel for handling prefetches associated with requests from the first processor, and a second channel for handling prefetches associated with requests from the second processor.

Title
Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors
Application Number
7/890859
Publication Number
4853846
Application Date
July 29, 1986
Publication Date
August 1, 1989
Inventor
Keith S Self
Aloha
OR, US
Steven R Page
Hillsboro
OR, US
Manfred Neugebauer
Erlangen
DE
Joel C Huang
Portland
OR, US
Ronald J Ebersole
Beaverton
OR, US
David B Johnson
Portland
OR, US
Agent
Owen L Lamb
Assignee
Intel Corporation
CA, US
IPC
G06F 12/12
G06F 12/08
G06F 12/02
G06F 12/00
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