04827428 is referenced by 103 patents and cites 4 patents.

A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element's size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path's timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.

Title
Transistor sizing system for integrated circuits
Application Number
6/798557
Publication Number
4827428
Application Date
November 15, 1985
Publication Date
May 2, 1989
Inventor
John P Fishburn
North Plainfield
NJ, US
Alfred E Dunlop
New Providence
NJ, US
Agent
Henry T Brendzel
Assignee
American Telephone and Telegraph Company AT&T Bell Laboratories
NJ, US
IPC
G06F 15/60
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