04819154 is referenced by 138 patents and cites 17 patents.

Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity.

To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks. Additional special-purpose hardware simultaneously invalidates all cache memory entries so that a new task can be loaded and started.

Title
Memory back up system with one cache memory and two physically separated main memories
Application Number
448419
Publication Number
4819154
Application Date
December 4, 1986
Publication Date
April 4, 1989
Inventor
James M Nolan Jr
Holliston
MA, US
Michael J Budwey
Holliston
MA, US
Jack J Stiffler
Concord
MA, US
Agent
Wolf Greenfield & Sacks
Assignee
Sequoia Systems
MA, US
IPC
G06Z 11/16
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