04814286 is referenced by 30 patents and cites 14 patents.

An electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the folating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.

Title
EEPROM cell with integral select transistor
Application Number
9998
Publication Number
4814286
Application Date
May 9, 1988
Publication Date
March 21, 1989
Inventor
Simon M Tam
San Mateo
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
H01L 29/78
H01L 29/94
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