04811215 is referenced by 47 patents and cites 3 patents.

An instruction execution accelerator for a pipelined digital machine with virtual memory. The digital machine includes a pipelined processor which on memory accesses outputs a virtual address to a data cache unit (DCU). On particular memory accesses, such as store or similar operations, the pipelined processor can be advanced or accelerated to the next instruction once the memory access is known not to cause a page fault. The pipeline accelerator includes a small associative memory which the page number of a target address of a store operation is compared. If there is a match, it is know that the target address relates to a page within the real memory and the instruction can complete asynchronously. Otherwise if there is no match, the page address is inserted in the associative memory to become the most recent addition. On the recognition of a page fault by the DCU, the associative memory will be cleared to make room for the new entry and others. The instruction execution accelerator can also be used for load instructions. If an address match is found on a load instruction, then the pipeline can be advanced to the next instruction, and must wait for the completion of the present load instruction only when another instruction attempts to reference the data prior to its being loaded.

Title
Instruction execution accelerator for a pipelined digital machine with virtual memory
Application Number
6/941085
Publication Number
4811215
Application Date
December 12, 1986
Publication Date
March 7, 1989
Inventor
Alan J Smith
Berkeley
CA, US
Agent
James A Deland
Robert C Colwell
Stephen J Phillips
Assignee
Intergraph Corporation
AL, US
IPC
G06F 9/00
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