04811214 is referenced by 221 patents and cites 29 patents.

A multinode parallel-processing computer is made up of a plurality of innerconnected, large capacity nodes each including a reconfigurable pipeline of functional units such as Integer Arithmetic Logic Processors, Floating Point Arithmetic Processors, Special Purpose Processors, etc. The reconfigurable pipeline of each node is connected to a multiplane memory by a Memory-ALU switch NETwork (MASNET). The reconfigurable pipeline includes three (3) basic substructures formed from functional units which have been found to be sufficient to perform the bulk of all calculations. The MASNET controls the flow of signals from the memory planes to the reconfigurable pipeline and vice versa. the nodes are connectable together by an internode data router (hyperspace router) so as to form a hypercube configuration. The capability of the nodes to conditionally configure the pipeline at each tick of the clock, without requiring a pipeline flush, permits many powerful algorithms to be implemented directly.

Title
Multinode reconfigurable pipeline computer
Application Number
6/931549
Publication Number
4811214
Application Date
November 14, 1986
Publication Date
March 7, 1989
Inventor
Michael G Littman
Philadelphia
PA, US
Daniel M Nosenchuck
Mercerville
NJ, US
Agent
Richard C Woodbridge
Assignee
Princeton University
NJ, US
IPC
G06F 15/16
G06F 9/00
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