04811082 is referenced by 428 patents and cites 1 patents.

A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.

Title
High performance integrated circuit packaging structure
Application Number
6/929946
Publication Number
4811082
Application Date
November 12, 1986
Publication Date
March 7, 1989
Inventor
Henri D Schnurmann
Monsey
NY, US
Burhan Ozmat
Peekskill
NY, US
Perwaiz Nihal
Hopewell Junction
NY, US
Scott L Jacobs
Chester
VA, US
Agent
Aziz M Ahsan
Steven J Meyers
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 23/12
H01L 23/02
H01L 39/02
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