A sampled synchronous transmission signal Vt is represented by a series of samples J at equidistant sampling instants. A computing circuit 5 computes the positions R of the sampling instants relative to the rising edges of a virtual reference clock Cref which is phase-locked to the channel clock. For each sampling instant the position R is determined on the basis of the position R of a preceding sampling instant and a measure Q of the difference in time between the sampling interval T and the period L of the virtual reference clock Cref. From the values of the successive samples J an interpolation circuit 2 derives the positions N of the detection-level crossings by the transmission signal Vt, which crossings represent a fixed phase position of the channel clock. After each detection-level crossing the measure Q of the time difference is corrected by circuit 3 and 4, depending on the difference between the positions N and R. A data recovery circuit arrangement recovers the data depending on the values determined for the positions R.