04807115 is referenced by 339 patents and cites 10 patents.

An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, instructions do no have to be issued according to their order in the instruction stream, so that non-sequential instruction issuance occurs. In this system, multiple instruction issuance and non-sequential instruction issuance policies enhance the throughput of processors with multiple functional units.

Title
Instruction issuing mechanism for processors with multiple functional units
Application Number
539854
Publication Number
4807115
Application Date
October 14, 1987
Publication Date
February 21, 1989
Inventor
Hwa C Torng
Ithaca
NY, US
Agent
Sughrue Mion Zinn Macpeak & Seas
Assignee
Cornell Research Foundation
NY, US
IPC
G06F 13/00
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