04802085 is referenced by 41 patents and cites 6 patents.

A method for detecting and handling memory-mapped I/O in a pipelined data processing system is provided. The method uses two signals on the system interface: when the system generates a read bus cycle, it activates an output signal if certain I/O requirements are not satisfied; an input signal is activated when the reference is to a peripheral device that exhibits certain characteristics; when the system detects that both the input signal and the output signal are active, it discards the data read during the bus cycle, serializes instruction execution and regenerates the read bus cycle, this time satisfying the requirements for I/O such that the output signal is driven inactive.

Title
Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor
Application Number
7/6012
Publication Number
4802085
Application Date
January 22, 1987
Publication Date
January 31, 1989
Inventor
Donald B Alpert
Herzlia
IL
Simon J Levy
Kfar Saba
IL
Agent
Limbach Limbach & Sutton
Assignee
National Semiconductor Corporation
CA, US
IPC
G06F 3/00
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