A programmable logic array device basically comprising a programmable AND gate array (FIGS. 5, 11) having addressable rows (40-45) and columns (32-38) or memory cells (30, 31) which can be individually programmed to represent logic data; an input signal receiving circuit (FIG. 9) for developing a corresponding buffered input signal; a first row driver (FIG. 10) responsive to the buffered signal and operative to cause a particular row of memory cells in an AND array (FIG. 11) to output corresponding logical product of AND-input signals, OR/NOR sensing circuitry (FIG. 12) for sensing the AND array product signals and for developing therefrom corresponding logical OR sum signals; circuit means output terminal circuitry; output switching circuitry (FIG. 14) responsive to a control signal and operative to couple either the circuit means output signal or a registered (FIG. 13) output to a device input or output terminal (FIG. 16); feedback switching circuitry similarly responsive to a control signal and operative to couple either the circuit means output signal, registered output signal, or feedback signal to a row driver; and Reprogrammable Architecture control circuitry (FIG. 24) to provide control signals to said switching circuitry. The device has the advantages of increased density of useable logic functions, and decreased power consumption.