04766564 is referenced by 12 patents and cites 12 patents.

A data processing system includes multiple floating point arithmetic units, for example, an adder and a multiplier. Two putaway busses and two bypass busses are connected to a register file and waiting stages, associated with the arithmetic units, respectively. A special source register is included for keeping track of the source of any result on the busses so that the registers may be connected to the appropriate bus on which the result is to appear in accordance with a busy or mark bit set in each register in the file and in the waiting stage. This allows multiple data items to exit the pipes during any cycle. Therefore, two or more results are produced each cycle.

Title
Dual putaway/bypass busses for multiple arithmetic units
Application Number
6/639754
Publication Number
4766564
Application Date
August 13, 1984
Publication Date
August 23, 1988
Inventor
Richard D DeGroot
Yorktown Heights
NY, US
Agent
Terry J Ilardi
Jack M Arnold
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 7/38
View Original Source