04755930 is referenced by 143 patents and cites 17 patents.

A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.

Title
Hierarchical cache memory system and method
Application Number
6/749581
Publication Number
4755930
Application Date
June 27, 1985
Publication Date
July 5, 1988
Inventor
Steven J Frank
Southboro
MA, US
Andrew W Wilson Jr
Pittsburgh
PA, US
Agent
Henry D Pahl Jr
Assignee
Encore Computer Corporation
MA, US
IPC
G06F 12/12
G06F 12/08
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