04745544 is referenced by 148 patents and cites 2 patents.

An array processor operating in the forced I/O mode includes a master controller (12) for generating sequenced commands for output to slave address generators (52) (54) and (62). The slave (52) and (54) operate in a data processing and a forced I/O mode. Each of the slaves have a set of data instructions and a set of I/O instructions therein. The data instructions are sequenced through in accordance with the sequenced commands generated by the master controller (12) synchronously and in parallel with the other slaves to generate addresses for memories (76) and (80). The master controller (12) initiates the I/O mode with runs independent and asychronously with respect to the sequenced commands to interface with an external I/O device (98). This data is transferred to the associated data memory and, when full, the operation alternates such that the other slave is in the I/O mode and the other data memory is utilized for storing I/O data.

Title
Master/slave sequencing processor with forced I/O
Application Number
6/809095
Publication Number
4745544
Application Date
December 12, 1985
Publication Date
May 17, 1988
Inventor
John P Shanklin
Colorado Springs
CO, US
Karl Renner
Dallas
TX, US
Agent
Melvin Sharp
Thomas W DeMond
Kenneth C Hill
Assignee
Texas Instruments Incorporated
TX, US
IPC
G06F 15/16
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