04734852 is referenced by 53 patents and cites 3 patents.

A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data from a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded. Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the register file. Logic circuitry detects storage of data prior to its writing back, so as to effectively replace the register file location. During page faults, the contents of the channel address, channel data, and channel control registers are saved to permit page fault recovery.

Title
Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
Application Number
6/771435
Publication Number
4734852
Application Date
August 30, 1985
Publication Date
March 29, 1988
Inventor
Ole Moller
Nivaa
DK
Cheng Gang Kong
San Jose
CA, US
Rod G Fleck
Mountain View
CA, US
William M Johnson
San Jose
CA, US
Agent
J Vincent Tortolano
Kenneth B Salomon
Patrick T King
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 12/00
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