04717681 is referenced by 105 patents and cites 21 patents.

A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

Title
Method of making a heterojunction bipolar transistor with SIPOS
Application Number
6/864671
Publication Number
4717681
Application Date
May 19, 1986
Publication Date
January 5, 1988
Inventor
Patrick A Curran
Plano
TX, US
Agent
Mel Sharp
N Rhys Merrett
Gary C Honeycutt
Assignee
Texas Instruments Incorporated
TX, US
IPC
H01L 29/72
H01L 21/265
View Original Source