04710903 is referenced by 91 patents and cites 1 patents.

A memory subsystem comprises pseudo-static memory chips operable in a low power self refresh mode or in a standby mode in which less access time is required. All memory chips are initially placed in the self refresh mode and are changed to the standby mode only when individually accessed. Then, the accessed chip is retained in the standby mode until such time as all chips are periodically returned to the self refresh mode. When a memory chip is first changed to the standby mode a delay time is provided to allow for the greater required access time. Thereafter, the memory chips which have then been placed in the standby mode are tracked by latching of addresses and comparison of the latched addresses to subsequently received addresses.

Title
Pseudo-static memory subsystem
Application Number
6/846328
Publication Number
4710903
Application Date
March 31, 1986
Publication Date
December 1, 1987
Inventor
Patricia A Martin
Westford
MA, US
Michael R Hereth
Westford
MA, US
Agent
Michael H Shanahan
Assignee
Wang Laboratories
MA, US
IPC
G11C 11/40
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