A passivated dual dielectric gate system compatible with low temperature processing utilizes a dual dielectric system with a silicon dioxide dielectric film or layer at the monocrystalline substrate surface, or termination. The dual dielectric system includes a dielectric film at the substrate surface of thicknesses of from 200 to 1000 .ANG.(or greater ). Respective layers of undoped amorphous silicon and titanium nitride overlie the top of the silicon dioxide and an aluminum gate metal layer overlies the titanium nitride layer. The structure can be patterned by selectively patterning photoresist and a dry or dry/wet etch processses. The structure is patterned and etched as desired. The system has enhanced surface mobilities due to lower oxide fixed charge density and smoother, more abrupt dielectric/monocrystalline interface region, is applicable to wide variety of MOSFET applications, and is inherently less electrostatic discharge (ESD) sensitive than conventional gate structures due to the distributed electric field.