04704785 is referenced by 115 patents and cites 15 patents.

A process, and product made thereby, for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafers having substantially the same crystal orientation and periodicity. A crystalline boundary n-semimetal is formed on the wafers, which are then brought into intimate contact. If desired, a unipolar conductor is fused to one of said wafers. Then, the wafers are exposed to an elevated temperature, or rapid thermal anneal, in an inert ambient, breaking up any native oxides and diffusing any excess oxygen into the wafer lattices. The guest wafer is then mechanically lapped back and chemically etched.

A vertical cascode integrated half H-bridge motor driving circuit made in the guest and host wafers has a source transistor in the host wafer with with the wafer substrate forming the collector of the transistor, an isotype acceptor doped Ge.sub.x Si.sub.l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming a compositional emitter, and with an n-semimetal boundary. The sink transistor of the guest is made with the wafer substrate forming the emitter, an isotype acceptor doped Ge.sub.x Si.sub.l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming the compositional collector. The guest substrate is terminated with an n-semimetal boundary. A buried conductor contacts the collector of the host transistor and the emitter of the guest transistor.

Title
Process for making a buried conductor by fusing two wafers
Application Number
6/893437
Publication Number
4704785
Application Date
August 1, 1986
Publication Date
November 10, 1987
Inventor
Patrick A Curran
Plano
TX, US
Agent
Melvin Sharp
Rhys Merrett
Gary C Honeycutt
Assignee
Texas Instruments Incorporated
TX, US
IPC
H01L 21/40
H01L 21/385
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