04698760 is referenced by 108 patents and cites 4 patents.

A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power-performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.

Title
Method of optimizing signal timing delays and power consumption in LSI circuits
Application Number
6/741922
Publication Number
4698760
Application Date
June 6, 1985
Publication Date
October 6, 1987
Inventor
Robert R Williams
Rochester
MN, US
Steven D Lewis
Rochester
MN, US
Robert F Lembach
Rochester
MN, US
Agent
Paul L Sjoquist
Assignee
International Business Machines
NY, US
IPC
G06F 15/60
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