04695950 is referenced by 44 patents and cites 8 patents.

A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

Title
Fast two-level dynamic address translation method and means
Application Number
6/651491
Publication Number
4695950
Application Date
September 17, 1984
Publication Date
September 22, 1987
Inventor
Timothy R Marchini
Wappingers Falls
NY, US
Wan L Leung
Coral Springs
FL, US
Patrick M Gannon
Poughkeepsie
NY, US
Henry R Brandt
Poughkeepsie
NY, US
Agent
Bernard M Goldman
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 12/10
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