04695943 is referenced by 84 patents and cites 11 patents.

A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

Title
Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization
Application Number
6/655473
Publication Number
4695943
Application Date
September 27, 1984
Publication Date
September 22, 1987
Inventor
Thomas F Joyce
Westford
MA, US
James W Keeley
Hudson
NH, US
Agent
John S Solakian
Faith F Driscoll
Assignee
Honeywell Information Systems
MA, US
IPC
G11C 7/00
G06F 13/00
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