04691281 is referenced by 25 patents and cites 3 patents.

In a data processing system for use in carrying out address translation of a preselected logical address so as to access a sequence of data elements stored in a memory (32) with an interval left between two adjacent ones of the data elements, a request control circuit (40) decides an element number in each cycle with reference to a logical distance (D) determined by the interval. The memory can be accessed in each cycle by a plurality of real addresses which are equal in number to the element number and which are calculated from the logical distance and the preselected logical address. Preferably, an address translation unit (80) is supplied with the preselected logical address and a part of the logical distance to produce a plurality of consecutive real page addresses (RPE and RPO) one of which corresponds to the preselected logical address. An address generator (50) produces a predetermined number of local logical addresses (EA.sub.0 .about.EA.sub.3) in response to the logical distance and the preselected logical address. The local logical addresses are combined with the consecutive real page addresses in an address combination circuit (100 ) to form local real addresses equal in number to the predetermined number. The local real addresses are restricted in number to the element number by a memory access controller (135) to be supplied to the memory as the real addresses.

Title
Data processing system simultaneously carrying out address translation of a plurality of logical addresses
Application Number
6/599869
Publication Number
4691281
Application Date
April 13, 1984
Publication Date
September 1, 1987
Inventor
Toshiyuki Furui
Tokyo
JP
Agent
Sughrue Mion Zinn Macpeak and Seas
Assignee
NEC Corporation
JP
IPC
G06F 12/10
View Original Source