04683547 is referenced by 19 patents and cites 8 patents.

A data processing system includes a multiple floating point arithmetic unit with a putaway and a bypass bus, which includes a new instruction for handling multiple multiply or divide instructions. These instructions are separated by add operations, including passing the results of each multiply/divide operation on a bypass bus to the input of an adder along with the inputs from an accumulate bypass bus which is the output from the adder for an automatic add operation on an accumulate multiply or accumulate divide operation. This allows two floating point results to be produced each cycle, one of which can be accumulated without any intervening control by the central decoder. The accumulation is performed under distributed control of the accumulator logic itself.

Title
Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance
Application Number
6/664739
Publication Number
4683547
Application Date
October 25, 1984
Publication Date
July 28, 1987
Inventor
Richard D DeGroot
Yorktown Heights
NY, US
Agent
Jack M Arnold
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 7/38
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