A memory subcontroller (203) of a computer (100) includes a queue (301) for storing read and write requests issued by memory using units (101-103) to a memory (104), apparatus (303, 304) for executing requests on the memory, and a circuit (302) for administering the queue. When the queue is empty and the executing apparatus is ready to receive a request for execution, a request incoming from a using unit bypasses the queue: it is received by the executing apparatus directly and is not stored in the queue. Otherwise, the queue administration circuit stores the request in the queue and then awaits results of validity checks on the stored request. If the request is found to be invalid, generally the administration circuit discards the request from the queue by freeing the queue location (210) or locations that store the invalid request to store the next received request. The invalid request is then overwritten by the next received request.