04677735 is referenced by 52 patents and cites 8 patents.

The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

Title
Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
Application Number
613679
Publication Number
4677735
Application Date
January 9, 1986
Publication Date
July 7, 1987
Inventor
Satwinder D S Malhi
Richardson
TX, US
Agent
Mel Sharp
Assignee
Texas Instruments Incorporated
TX, US
IPC
H01L 21/425
View Original Source