04673891 is referenced by 13 patents and cites 2 patents.

A Frequency synthesis stage comprises two phase locked loops. The first (O.sub.1, D.sub.1, M, CP.sub.1, D.sub.2) divides the frequency Fo+.DELTA. derived from preceding stages by N/Q, N being a variable integer, and adds to the result a standard frequency P which is in a fixed ratio with a value representative of large frequency steps so as to give an intermediate frequency F.sub.A, while the second (O.sub.2, M.sub.0, M.sub.1, CP.sub.2 D.sub.3) multiplies F.sub.A by NQ/r. P and Q are selected so that the product PQ is approximately equal to the mean of the limit values desired for the output frequency.

Title
Frequency synthesizer having first phase locked loop frequency multiplied by near unity in second phase locked loop
Application Number
6/787191
Publication Number
4673891
Application Date
October 15, 1985
Publication Date
June 16, 1987
Inventor
Joel Remy
Paris
FR
Agent
William A Drucker
Assignee
Adret Electronique
FR
IPC
H03L 7/22
H03L 7/18
View Original Source