04667326 is referenced by 122 patents and cites 5 patents.

A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.

Title
Method and apparatus for error detection and correction in systems comprising floppy and/or hard disk drives
Application Number
6/685018
Publication Number
4667326
Application Date
December 20, 1984
Publication Date
May 19, 1987
Inventor
Michael C Shebanow
Berkeley
CA, US
John Drew
Los Gatos
CA, US
Mark S Young
Mountain View
CA, US
Agent
J Vincent Tortolano
Warren M Becker
Patrick T King
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 11/16
G06F 11/08
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