A video memory and display (CRT) controller circuit on a single semiconductor substrate controls a DRAM (dynamic random access memory) used as a video memory and a CRT display. The video memory and display controller is normally a part of a video system which includes a data processor, video memory and a CRT display. The video memory and display controller includes a row address latch for storing a row address, a column address latch for storing a column address, display address logic which generates row and column addresses for display update ad refresh logic which generates row addresses for the required periodic DRAM refresh. A multiplexer provides the application of the proper address to the address bus of the DRAM. The display controller circuit is responsive to the data processor data bus for generating display control signals for control of the CRT display.