04654777 is referenced by 40 patents and cites 7 patents.

An address translation system is provided which has a real storage, a virtual storage having a "V.dbd.R" segment (first segment), second segments to be subjected to two-level paging, and page table segments (third segments) to be used as a page table corresponding to the second segments, a segment table, a first page table which corresponds to the second segments, a second page table which corresponds to the page table segments, and a memory control unit having a virtual address register and a microprocessor for translating the virtual address in the virtual address register into a real address. By means of microprogram control, the microprocessor has a first address translation function for obtaining a real address from the page number and the displacement data of the virtual address if the segment number of the virtual address represents the first segment, a segment table referring function for referring to the segment table based on the segment number if the segment number does not represent the first segment, and a second address translation function for referring to the second page table based on the reference result from the segment table and the several most significant bits of the page number, for referring to the first page table based on the reference result of the second page table and on the remaining bits of the page number, and for obtaining the real address from the reference result of the first page table and the displacement data.

Title
Segmented one and two level paging address translation system
Application Number
6/495615
Publication Number
4654777
Application Date
May 18, 1983
Publication Date
March 31, 1987
Inventor
Hiroshi Nakamura
Tokorozawa
JP
Agent
Cushman Darby & Cushman
Assignee
Tokyo Shibaura Denki Kabushiki Kaisha
JP
IPC
G06F 12/10
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