04641305 is referenced by 21 patents and cites 5 patents.

A method and apparatus for a microinstruction controlled unit to recover from a read error in reading microinstructions from a control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. Execution of the current microinstruction is begun before it is known whether or not it was read without error. The apparatus provides for aborting the execution of the current microinstruction with the read error and the next microinstruction. During the aborted execution of the next microinstruction, the current microinstruction is reread from the control store and then executed while the next microinstruction is being reread. The execution of microinstructions is aborted in a manner that does not alter the state of the microinstruction controlled unit beyond the point that would inhibit the re-execution of the aborted microinstructions.

Title
Control store memory read error resiliency method and apparatus
Application Number
6/663101
Publication Number
4641305
Application Date
October 19, 1984
Publication Date
February 3, 1987
Inventor
Richard P Kelly
Nashua
NH, US
Thomas F Joyce
Westford
MA, US
Agent
John S Solakian
George Grayson
Assignee
Honeywell Information Systems
MA, US
IPC
G06F 11/14
G06F 11/10
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