04639899 is referenced by 1 patents and cites 2 patents.

A memory circuit for storing data words including a core memory having a matrix of rows and columns of core cells which store bits of the data words, a row address decoder circuit for driving the rows, and a control signal generator, operative over one reset period and one recovery period, for controlling the columns and the row address decoder circuit to simultaneously charge the contents of the entire core memory to one data state.

Title
Memory circuit having a memory reset and recovery controller
Application Number
6/536920
Publication Number
4639899
Application Date
September 27, 1983
Publication Date
January 27, 1987
Inventor
Guey T Lu
San Jose
CA, US
Colin N Murphy
San Mateo
CA, US
Agent
Warren Becker
Martin C Fliesler
Patrick T King
Assignee
Advanced Micro Devices
CA, US
IPC
G11C 11/40
G11C 7/00
View Original Source