04638187 is referenced by 174 patents and cites 1 patents.

A CMOS output buffer provides high drive current without sacrificing speed and with minimum output signal distortion due to internal chip ground bounce or output signal ringing. The output buffer includes a pull-up circuit and a pull-down circuit which distribute switching current spikes over time. The pull-up circuit includes a P-channel FET and an N-channel FET connected in parallel between an output terminal and supply terminal V.sub.DD, with an inverter connected between the gates of the N-channel and P-channel FETs to provide the proper phase for the P-channel FET as well as delaying turn-on of the P-channel FET with respect to turn-on of the N-channel FET. The pull-down circuit includes a pair of N-channel FETs connected in parallel between the output terminal and ground, and a delay resistance connected between their gates so that turn-on of one of the N-channel FETs is delayed with respect to the other.

Title
CMOS output buffer providing high drive current with minimum output signal distortion
Application Number
6/782639
Publication Number
4638187
Application Date
October 1, 1985
Publication Date
January 20, 1987
Inventor
Gene B Zemske
Minneapolis
MN, US
Surinder S Rai
Plymouth
MN, US
William W Leake
St. Paul
MN, US
Clifford H Boler
Bloomington
MN, US
Agent
Kinney & Lange
Assignee
VTC Incorporated
MN, US
IPC
H03K 21/10
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