04635261 is referenced by 65 patents and cites 8 patents.

An on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation. The system is integrated on a chip that includes a plurality of inputs and a plurality of outputs. A plurality of gates are coupled between the plurality of inputs and outputs wherein input signals may be transmitted asynchronously to the gates and output signals may be transmitted asynchronously to the outputs. An input shift register is coupled between each of the inputs and the gates for synchronously transmitting input signals, and an output shift register is coupled between the gates and each of the outputs for synchronously transmitting output signals. A control logic circuit is coupled to the plurality of gates, the input shift registers, and the output shift registers for selecting the systems mode of operation. A comparator circuit is coupled to the output shift registers for comparing said output signals with expected signals.

Title
On chip test system for configurable gate arrays
Application Number
6/748885
Publication Number
4635261
Application Date
June 26, 1985
Publication Date
January 6, 1987
Inventor
Liang Tsai Lin
San Diego
CA, US
Floyd E Anderson
Round Rock
TX, US
Agent
William E Koch
Assignee
Motorola
IL, US
IPC
G01R 31/28
View Original Source