04631724 is referenced by 44 patents and cites 5 patents.

A semiconductor tester in which an address is generated by a test pattern generator in synchronism with an operating clock from a timing generator, the address is applied to a memory under test, and a check is made to determine if the power source current to the memory under test is larger than a predetermined value. A current value deciding circuit is provided, by which the power source current value is detected, and it is decided by a comparator whether the detected current value is greater than the predetermined value or not. The decision result is output at the timing of an output timing signal from the timing generator.

Title
Semiconductor memory test equipment
Application Number
6/734109
Publication Number
4631724
Application Date
May 15, 1985
Publication Date
December 23, 1986
Inventor
Masao Shimizu
Gyoda
JP
Agent
Staas & Halsey
Assignee
Advantest
JP
IPC
G01R 31/28
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