04621363 is referenced by 36 patents and cites 4 patents.

The detailed testing of processors, manufactured according to very large scale integration principles, which also extends to secondary functions of operations, such as the setting or non-setting of particular state indicators, necessitates the transfer of large quantities of test data between the processor and the tester, for which purpose no distinction is drawn between external and integrated testers. For testing such structures, the known LSSD method is frequently used wherein the storage elements of the logic subsystems are combined in the form of shift register chains for testing. To permit a fast exchange of test data on the system bus, connecting the processor to a tester, interface register stages are also included in the shift register chain which has a garland-shaped structure and whose beginning and end are connected by a controllable switch during testing. During testing, the entry of test data and the emission of result data, which are in each case effected through the system bus and the shift steps of the garland-shaped shift register chain, overlap one another.

Title
Testing and diagnostic device for digital computers
Application Number
6/678750
Publication Number
4621363
Application Date
December 6, 1984
Publication Date
November 4, 1986
Inventor
Arnold Blum
Gechingen
DE
Agent
Saul S Seinberg
John H Bouchard
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 11/00
G01R 31/28
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