04621339 is referenced by 153 patents and cites 10 patents.

A single instruction, multiple data stream parallel computer using bit-serial arithmetic whereby the machine's basic operation is performing Boolean operations on huge vectors of 0's and 1's. The machine utilizes an architectural approach whereby the memory of a conventional machine having 2.sup.k words each t bits long, is reorganized into p registers each 2.sup.k bits in length and adding processor logic to each bit position of the registers and a communication network being added which allows for the 2.sup.k pieces of processing logic to interact. This machine is capable of executing a wide variety of algorithms at a speed of 2.sup.k /p to 2.sup.k /p.sup.2 faster than conventional machines. The machine provides for an ability to handle a variety of algorithms by interconnecting the individual processor elements in a general interconnection network capable of performing a permutation of n bits held one in every processor element in a time of (O(log(n)).

Title
SIMD machine using cube connected cycles network architecture for vector processing
Application Number
6/503654
Publication Number
4621339
Application Date
June 13, 1983
Publication Date
November 4, 1986
Inventor
Charles J Poirier
Red Bank
NJ, US
Robert A Wagner
Durham
NC, US
Agent
Oblon Fisher Spivak McClelland & Maier
Assignee
Duke University
NC, US
IPC
G06F 15/16
View Original Source