A logic decoder provides a true output signal at a first logic state when selected during an active cycle and during an inactive cycle, and at a second logic state when deselected. The logic decoder also provides a complementary output signal. A word line driver circuit couples decoded address signals to respective word lines when the output signal is in the first logic state. A coupling circuit couples one of first and second word lines to ground during the active cycle. A coupling transistor couples the first and second word lines together in response to receiving the complementary output signal at the first logic state.