04615102 is referenced by 41 patents and cites 7 patents.

A semiconductor device, which comprises an E-mode FET and a D-mode FET and utilizes a two-dimensional electron gas, comprises a semi-insulating semiconductor substrate, a channel layer, an electron-supply layer, a third layer, a first etching-stoppable layer, a fifth layer, and a second etching-stoppable layer, which layers are formed in sequence on the substrate. An etching process for forming grooves of gate electrodes of the FETs comprises a first etching treatment removing the first etching-stoppable layer portion in the E-mode FET region and the second etching-stoppable layer portion in the D-mode FET region, and a second etching treatment removing the third layer portion in the E-mode FET region and the fifth layer portion and using an etchant different from that used in the first etching treatment. In the second etching treatment, reactive ion etching method using a CCl.sub.2 F.sub.2 etchant gas is adopted, since GaAs can be thereby rapidly etched as compared with AlGaAs used for the etching-stoppable layer material.

Title
Method of producing enhancement mode and depletion mode FETs
Application Number
6/728080
Publication Number
4615102
Application Date
April 29, 1985
Publication Date
October 7, 1986
Inventor
Takashi Mimura
Machida
JP
Masahisa Suzuki
Sagamihara
JP
Agent
Armstrong Nikaido Marmelstein & Kubovcik
Assignee
Fujitsu
JP
IPC
H01L 21/205
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