A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations are carried out by passing the product of the operands successively through an array of adders in the Adder unit 34. Each adder adds an appropriate multiple of the contents of the X Register to the Accumulator 40 or to the output of the previous adder. The multiples are selected according to the contents of the Y Register.
The X and Y Registers are fully buffered so that additional data transfers and functions may be performed while an arithmetic operation is in progress in a "pipeline" manner.
The circuit is also capable of indicating the maximum or minimum value in a sequence of numbers in response to a single computer instruction to the circuit.