04593363 is referenced by 142 patents and cites 11 patents.

For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas of decreasing size, the set of components is partitioned into subsets which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.

Title
Simultaneous placement and wiring for VLSI chips
Application Number
6/522900
Publication Number
4593363
Application Date
August 12, 1983
Publication Date
June 3, 1986
Inventor
Richard N Pelavin
Chappaqua
NY, US
Se J Hong
Yorktown Heights
NY, US
Michael Burstein
Carmel
NY, US
Agent
Thomas P Dowd
Jack M Arnold
George E Clark
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 15/20
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