Applicant processes to be performed on several processors in a data processing system are synchronized and allocated. The data processing system includes plural processors, each of which derives a control signal indicating that an event has occurred which requires a change in the status of the system, as well as registers for storing signals indicative of a process being executed by the processor. A memory common to the processors is selectively coupled to the processors via a bus. A circuit connected to the memory, the bus and selectively coupled to the processors selectively couples signals between a selected processor and the memory via the bus. The applicant processes are allocated and synchronized by a first circuit responsive to the control signal that allocates one of the processors to an applicant process and by second circuit that couples signals for the process being executed by the allocated processor at the time the control signal is coupled to the allocated process from the registers of the allocated processor to the memory via the data bus which thereafter couples signals for the applicant process from the memory to the registers of the allocated processors via the bus.