04577276 is referenced by 117 patents and cites 1 patents.

In laying out integrated circuits on a substrate, the placement of the components relative to each other is important in minimizing conductor area and hence chip area. Large scale integration often uses polycells which are lined up in rows to realize the digital logic circuitry. A partitioning procedure is disclosed which iteratively separates the cells into maximally connected subcells, eventually to assign them to rows so as to minimize conductor area. A technique called terminal propagation takes into account at every iteration the location of connections outside of the partitioned area. Rectilinear Steiner trees are generated to aid in terminal propagation.

Title
Placement of components on circuit substrates
Application Number
6/531423
Publication Number
4577276
Application Date
September 12, 1983
Publication Date
March 18, 1986
Inventor
Brian W Kernighan
Berkeley Heights
NJ, US
Alfred E Dunlop
New Providence
NJ, US
Agent
Robert O Nimtz
Assignee
AT&T Bell Laboratories
NJ, US
IPC
G06F 15/46
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