04570220 is referenced by 124 patents and cites 1 patents.

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

Title
High speed parallel bus and data transfer method
Application Number
6/555027
Publication Number
4570220
Application Date
November 25, 1983
Publication Date
February 11, 1986
Inventor
Steven D Kassel
Aloha
OR, US
Edwin L Jacks Jr
Beaverton
OR, US
Sudarshan Balachandran
Aloha
OR, US
Alireza Sarabi
Hillsboro
OR, US
Robert L Farrell
Portland
OR, US
John Beaston
Hillsboro
OR, US
Raymond S Tetrick
Portland
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 15/16
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