04545028 is referenced by 8 patents and cites 1 patents.

A new technique for the accumulation of partial product terms in a monolithic VLSI multiplier is disclosed. The method requires fewer than a 5% increase in transistors over older techniques yet provides more than three times the performance of the prior art when used to implement a 64.times.64 multiplier. The accumulator is implemented with one-bit cells to facilitate the VLSI mask design and is expandable to any desired precision.

Title
Partial product accumulation in high performance multipliers
Application Number
6/434298
Publication Number
4545028
Application Date
October 13, 1982
Publication Date
October 1, 1985
Inventor
Frederick A Ware
Los Altos Hills
CA, US
Agent
Jeffery B Fromm
Assignee
Hewlett Packard Company
CA, US
IPC
G06F 7/52
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